1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a cell refresh circuit for a semiconductor memory device
2. Background of the Related Art
FIG. 1 is a block diagram showing the construction of a related art erasable programming read only memory (EPROM). As shown in FIG. 1, a related art EPROM includes a memory block 120 for storing an executable program, a power switching unit 110 and a sense amplifier 130. The power switching unit 110 selects and outputs to the memory block 120 a program voltage (Vpp) in a program mode or a source voltage (Vdd) in a normal operation mode in accordance with a program mode signal (WEPRM). The sense amplifier 130 outputs data on a data bus (DB) to the memory block 120 when a ROM write signal (RWR) is enabled in a program mode or transmits the data stored in the memory block 120 to the data bus (DB) when a ROM read signal (RRD) is enabled in a normal operation mode.
When the EPROM is disposed in a ROM writer and the program mode signal (WEPRM) is enabled, the power switching unit 110 selects the program voltage (Vpp) and applies it to the memory block 120. Then, when the ROM write signal (RWR) is enabled and addresses (A0, . . . , An) are accessed in the memory block 120, the sense amplifier 130 transmits a program carried on the data bus (DB) to the memory block 120 to store in a corresponding region. The operation for storing a program is repeatedly carried out to store the program in a corresponding region as addresses (A0, . . . , An), which are sequentially accessed in the memory block 120.
When the storage of the program in the EPROM is completed and the EPROM is disposed to operate a system, the program mode signal (WEPRM) is disabled and the power switching unit 110 selects the source voltage (Vdd) to apply to the memory block 120. When the ROM read signal (RRD) is enabled and the addresses (A0, . . . , An) are accessed in the memory block 120, the sense amplifier 130 reads out the data from the memory block 120 to transmit to the data bus (DB). Accordingly, a central processing unit (CPU can read a program carried on the data bus (DB) to execute a corresponding operation.
The related art EPROM, however, has various disadvantages. In the related art EPROM, the data programmed in the EPROM cell may be damaged with the lapse of time according to the characteristics of the EPROM cell. The damaged data in the EPROM cell can result in an unprogrammed state. Therefore, the reliability of the EPROM and operations of the system using EPROM cannot be ensured.